1. Field of the Invention
The present invention relates generally to capacitors in integrated circuits.
2. Background Art
Capacitors are fundamental component devices in many of today's communication integrated circuits (IC), including sample and hold circuits, analog to digital (A/D) converters, and radio frequency (RF) applications. Several types of capacitors are available in standard Complementary Metal Oxide Semiconductor (CMOS) logic and mixed signal technologies. Example capacitors include metal-insulator-metal (MIM) capacitor, Negative polarity Metal Oxide Semiconductor (NMOS) in Nwell MOS capacitors, Positive polarity Metal Oxide Semiconductor (PMOS) in Pwell capacitors, and metal line lateral and vertical flux capacitors.
Depending on the particular application, each capacitor type has its advantages and disadvantages in terms of performance and fabrication. For example, historically speaking, MIM capacitors could achieve greater capacitance densities compared to other types of capacitors, but during fabrication the MIM capacitors required an additional mask. More recently, since the density of metal-to-metal capacitors has become close to that of MIM capacitors, and since they do not require an additional mask, metal-to-metal capacitors are often used in RF applications.
The idea of a capacitor is simple: to store electrostatic energy between two dielectric volumes. The theoretical limitations on the capacitance that can be achieved in a capacitor is determined by the voltage difference between the two dielectric volumes and the geometric characteristics of the two dielectric volumes. Much of the effort in improving the capacitance of a capacitor used in an integrated circuit has focused on altering the geometric characteristics of the two dielectric volumes.
Several different geometrical designs for metal-to-metal capacitors have been disclosed in other publications. For example, Robert Aaricio and Ali Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors,” IEEE Journal of Solid-State Circuits, 37(3), (March 2002), present the following list of metal line capacitors that are used in communication IC applications: (i) parallel wire configuration, (ii) vertical parallel plate structure, (iii) quasi-fractal capacitor structure, (iv) vertical bar structure, and (v) Manhattan capacitor structure. In addition, Hirad Samavati et al, “Fractal Capacitors,” IEEE Journal of Solid-State Circuits, 33(12), (December 1998), discuss the use of (vi) fractal capacitors. Each of these capacitor configurations is briefly described below.
FIG. 1 shows a simple geometric design for a capacitor 100, which uses parallel plates held at different biases to store electrostatic energy. For example, plate 110 can be electrically high, while plate 120 can be electrically low. While this design can be used to effectively store electrostatic charge, it consumes a larger portion of the silicon chip compared to other geometrical designs making this an inefficient and undesirable capacitor design. Variations of the parallel plate capacitor abound.
FIG. 2 shows a lateral view 210 and a top view 220 of a capacitor in the parallel wire configuration. One portion of the parallel wire capacitor is held at a high bias and another portion is held at a low bias. For example, a portion 230 can be held at an electrically high bias, whereas another portion 240 can be held at an electrically low bias. A capacitor utilizing this configuration can improve capacitance density by taking advantage of both the lateral and vertical electric field components of each of portions 230 and 240.
FIG. 3 shows a capacitor 300 in the vertical parallel plates configuration. A vertical plate 310 can be held at an electrically high bias, whereas an adjacent vertical plate 320 can be held at an electrically low bias. Vias 330 connect the vertical wire-segments to create vertical slabs, e.g., vertical plate 310 or vertical plate 320.
FIG. 4 shows a three-dimensional lateral view 410 and a top view 420 of a capacitor in the vertical bars configuration. Metal squares are vertically connected by vias 450 to create columns of capacitor terminals, e.g., capacitor terminal 430 and capacitor terminal 440.
FIGS. 5A, 5B, 5C and 5D show various Manhattan structure capacitors 510, 520, 530 and 540, respectively. As these figures show, Manhattan structure capacitors are simple variations of different rectangular-shaped structures.
FIGS. 6A, 6B and 6C show various quasi-fractal capacitor structures 610, 620 and 630, respectively, and FIG. 7 shows a fractal capacitor design 710. Fractal and quasi-fractal structures are, theoretically speaking, good candidates for capacitor designs, because fractals fill more of a two-dimensional area than a simple curve does. Hence, fractal and quasi-fractal designs can potentially lead to higher capacitance density compared to other designs. However, due to fabrication processes a true fractal capacitor cannot be realized on an integrated circuit.
Although there are several types of metal-to-metal capacitors, as technology continues to scale, designs that optimize capacitance density and capacitance matching are the most desirable. Relatively speaking, capacitors occupy a large fraction of the chip area, so as chips shrink in size an increase in capacitance density is needed. Furthermore, in order for a capacitor to achieve proper performance within a given IC, it is important that the capacitance of adjacent components be fairly accurately matched; i.e. the measured capacitance of adjacent capacitor components should be almost identical. Current capacitor designs (e.g., the capacitors discussed with reference to FIGS. 1–4, 5A, 5B, 5C, 5D, 6A, 6B, 6C and 7) are less than ideal in terms of capacitance density and matching.
Therefore, further improvements in the capacitance density and capacitance matching are needed as technology scales. In addition, since process-induced variations tend to hamper the performance of capacitors, it would be advantageous if the improvements were achieved in a manner that minimized process-induced variations.